Concerning the size of the CMOS technology
The keyword：Art changes; Manufacturing defects; The transient error of scale;CMOS
In this paper：Methodologies for Adaptation to Process Variations, Manufacturing Defects, and Transient Errors in Scaled CMOS Abstract VLSI technology scaling has spurred a rapid growth in the semiconductor industry. With CMOS device dimensions falling below 100 nm, achieving higher performance and packing more complex functionalities into digital integrated circuits have become easier. However, the
scaling trend poses new challenges to design and process engineers. Such challenges include larger process parameter variations and the consequent parametric yield loss, ensuring the reliability of deep sub-micron technologies under soft errors, and reliably fabricating billions of devices on a die. The objective of my research has been to develop circuit and system level techniques to address process variations, transient errors, and the reliability concerns in deeply scaled CMOS technologies. The proposed techniques can be divided into three parts, highlighted in the next three sections. The first part addresses the issues related to process variations and proposes techniques to reduce the variation effects on power and performance. The second part proposes a novel low-overhead defect-tolerant approach for CMOS designs capable of efficiently recovering from dozens of defects. The third section deals with the
transient errors and techniques to reduce the effect of transient errors with minimum hardware or computational overhead.
1. Variation-Tolerant Design With the increase of process parameter variations in CMOS technologies due to the processing and masking limitations, power and
performance variations become major concerns of circuit designers. Techniques such as the use of forward/reverse body bias and voltage scaling are commonly used to bring down the delay and power consumption specifications in the acceptable range. Variation-aware circuit sizing is another technique used at the design stage to have a more variation-tolerant circuit. The key goal of this research is to provide techniques for designing more variation-tolerant circuits. We propose to attack the problem both at the design stage and at the post-fabrication stage. The latter requires the feasibility of having ways of specification tuning and a fast and efficient framework that makes the post-silicon tuning attractive. The summary of the proposed techniques is as follows: Variation-Aware Placement [1],[2]: In this work the huge leakage variation problem was addressed by looking at the effects that the gate placement have in leakage distribution. The work includes algorithms for the placement of gates in a dual-V circuit to mitigate the large leakage variation by reducing the variation caused by correlated within-die process variation. The experimental results on ISCAS benchmark circuits shows how by evenly distributing the low-V gates (which are more sensitive to variation sources such as the channel length variation) across a die, one could reduce the sub-threshold leakage variation as comparedto the placement technique with the objective of minimizing wire length. The results show that the sub-threshold leakage variation is reduced by an average of 17% and maximum of 31%. This obtained with a small increase in wire length. Post-Manufacture Tuning Architecture [3]: In this work, an architectural framework forpost-silicon performance testing and tuning to bring the delay of a die within the acceptable range was
developed. Also, a modified form of CMOS gate that can be programmed to work in a low-speed or a high-speed mode is presented. In the proposed architecture, specific hardware tuning “knobs” (control mechanisms) such as tunable gate supply voltage, or body bias can be employed to deal with the delay and leakage variation. These control mechanisms are actuated by a proposed efficient delay test method that
implicitly measures the delay of embedded logic circuits. A hardware framework that can support such self-test/self-adaptation is developed and algorithms are designed for optimizing the various enabling design parameters. This work covers different area from delay testing to low-level CMOS gate design of tunable gates. Simulation results show that using the proposed tunable gates on close-to-critical paths combined with the self-test/self-reconfiguration architecture can improve the delay yield by 40%. This is obtained with little increase in the power consumption
2. Defect-Tolerant CMOS Gate Design[4]. End-of-the-roadmap nano-scale CMOS is expected to suffer from significant defectivity due to manufacturing defects, random process variations, and wear-out. To ensure acceptable yield and reliable operation of the circuit during its life-time, future circuits must be equipped with a significant defect-tolerance capability. Traditional defect-tolerance approaches are too expensive to be applied to general purpose circuits. This work proposes a defect-tolerant CMOS logic gate architecture that exploits the inherent functional redundancy in the static
CMOS. This is accomplished by reconfiguring the CMOS logic gate to a
pseudo-NMOS-like gate in the presence of a defect. The proposed standard-cell-based defect-tolerant affects recovery in the presence of faulty transistors in the pull-up
P-network by reconfiguring into a pseudo-NMOS gate, replacing the faulty P-network with a single P transistor as a resistive pull up. Similarly, a fault in the N-network is recovered from by replacing the N-network by a properly sized single N transistor. The proposed gate design can tolerate multiple defects in either the pull-up or pull-down network. To minimize the routing overhead associated with the
reconfiguration, a grid-based two-dimensional routing methodology for control signals is proposed. The proposed control system can be implemented in the
poly-silicon layer with virtually no adverse impact on the availability of the metal layers for the functional interconnects. The effectiveness of the proposed
defect-tolerant technique and its impact on circuit delay and power is studied. It is shown that the technique imposes little delay overhead (less than 6%) but incurs leakage power dissipation overhead (less than 20%) in the presence of defects.
3. Probabilistic Checksum-Based Error Correction [5][6]. According to ITRS
2003, !°Relaxing the requirementof 100% correctness for devices and interconnects may dramatically reduce costs of manufacturing, verification and test. In another word, it is hard to achieve 100%correctness because of an increase in transient error rate. Such an increase is assumed to be driven by the aggressive technology scaling and is associated with the reduced noise margin, power/ground bounce,
radiation-induced effect, or because of permanent failures on internal signal lines that are excited intermittently by real-time stimulus. At the same time, the classical fault-tolerant techniques are all proven to be too costly to be used in non-critical
applications. Following this trend and the observation that for many DSP applications, it is not necessary to maintain a cycle-to-cycle accurate computation as long as the system level quality ofservice metrics are satisfied or degraded within acceptable levels, a real-time probabilistic compensation technique for DSP applications is proposed. The objective of technique is to improve the quality of service of the DSP application, using very little hardware overhead. The proposed probabilistic technique can compensate for errors in combinational circuits as well as the storage elements. Our simulation results on linear filters shows that by using the proposed technique, SNR improvements (up to 13 dB) can be obtained in the presence of soft errors
Reference ： 1. M. Ashouei, A. Chatterjee, A. D. Singh, and V. De, A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nano CMOS, International Conference on Circuit Design, Oct. 2005, pp. 567 ¨C 573. 2. M. Ashouei,
A. Chatterjee, A. D. Singh, V. De, and T.M. Mak, Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design, International Conference on VLSI Design, Jan. 2006, pp. 606 ¨C612. 3. M. Ashouei, M. Nisar, A. Chatterjee, A. D. Singh, A. Diril, Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations, International Conference on VLSI Design, Jan. 2007. 4. M. Ashouei, A. D. Singh, A. Chatterjee, A Defect-Tolerant Architecture for End-of-Roadmap CMOS, accepted to European Test Symposium, May 2007, Freiburg, Germany. 5. M. Ashouei, S. Bhattacharya, and A. Chatterjee, Probabilistic Compensation for Digital Filters under Pervasive
Noise-Induced Operator Errors, accepted in VLSI Test Symposium, May 2007. 6. M. Ashouei, S. Bhattacharya, and A. Chatterjee, Improving SNR for DSM Linear
Systems Using Probabilistic Error Correction and State Restoration: A Comparative Study, the European Test Symposium, May 2006, pp. 35 ¨C 42.
论规模的CMOS 技术
关键字：艺变化；制造 缺陷; 瞬态误差尺度的; CMOS 。
摘要 超大规模集成电路技术的推广已经刺激起了快速增长的半导体产业。随着 CMOS 器件尺寸低于 100 纳米， 实现更高的性能和更复杂的功能包装成数字集成电路变得更加容易。然而，扩大的趋势带来了新的挑战，以设计和工艺工程师。 这些挑战包括更大的工艺参数变化和由此产生的参数产量损失，为确保可靠性的深 亚微米技术下的软错误和可靠编造十亿设备的死亡的目标， 我的研究已发展集成电路和系统级技术解决过程中的变化， 瞬时的错误， 和可靠性深感关切规模的 CMOS 技术。拟议的技术可分为三个部分，强调在未来的三节。第一部分涉及的有关问题过程中的变化，并提出技术，以降低变化影响 的功率和性能。第二部分提出了一种新颖的低开销缺损容错办法的 CMOS 设计能够有效地从几十个缺陷。 第三部分涉及的是短暂的错误和技 术，以减少影响的瞬态最低硬件错误或计算开销。
1 。变异容错设计 随着工艺参数变化的 CMOS 技术由于处理和掩蔽的限制，功率和性能的变化成 为主要关注的电路设计技术，如使用前进/后退机构偏见和电压缩放常用来降 低延迟和功耗规格在可接受的范围内。 变异知道电路上浆用另一种方法是在设计 阶段有一个更变异性的赛道。 的主要目标，这项研究是提供技术，设计更变异的容错电路。我们建议把攻 击的问题在设计阶段，并在后加工阶段。后者要求具有可行性的方式，调整和规 范的快速和有效的框架，使后硅调谐吸引力。摘要拟议技术如下： 变异意识到放置[ 1 ] [ 2 ] ：在这项工作中的巨大变化渗漏处理的问题是看 效果，门口放置在泄漏分配。这项工作包括算法安置盖茨在双电压电路，以减轻 大的变化， 减少渗漏的变化所造成的相关内死亡过程的变化。 实验结果对 ISCAS 基准电路显示的均匀分布的低电压盖茨（这是更敏感的变化等来源渠道长度变 异）跨越死亡，一可以减少次临界渗漏的变化相比，安置技术的目标是尽量减少 导线长度。结果表明，次临界渗漏变异平均减少 17 ％和最高的 31 ％ 。这获 得了一个小增加线的长度。 邮政制造调整结构[ 3 ] ：在这项工作中，一个建筑框架后硅片性能测试和 调整，使拖延了模具可以接受的范围内制定。此外，修改后形成的 CMOS 栅极可 被编程工作在低速或高速模式时提出。 在拟议的结构，具体的硬件调节“旋钮” （控制机制） ，如可调门供电电压， 或机构的偏见可以用来处理拖延和渗漏变化。 这些控制机制驱动提议有效延迟测 试方法，含蓄措施拖延的嵌入式逻辑电路。硬件框架，可以支持这些 self-test/self-adaptation 是发达国家和算法设计的优化设计参数的各 种有利。这项工作涉及不同地区拖延测试低级别的 CMOS 栅极设计可调盖茨。仿 真结果表明，使用拟议的可调谐盖茨接近关键路径结合 self-test/self-reconfiguration 结构可以提高产量拖延了 40 ％ 。这 是获得很少增加耗电量
2 。缺陷容错 CMOS 栅极设计[ 4 ] 。 完型的路线图纳米级的 CMOS 预计将遭受重大 defectivity 由于制造缺陷， 随机过程的变化，和磨损程度。为了确保可接受的产量和可靠运行的电路在其生 命的时间，未来电路必须具备的一个重要缺陷容忍能力。传统的缺陷容忍办法过 于昂贵，适用于一般用途的电路。这项工作提出了一种缺陷性的 CMOS 逻辑门的 架构，利用固有的功能冗余的静态 CMOS 。这是通过改造 CMOS 逻辑门伪 NMOS 样闸门存在一个缺陷。 拟议的标准单元为基础的缺陷性影响复苏存在缺陷的晶体 管在拉个 P -网络通过改造成一个伪 NMOS 门，取代了错误的 P -网络与一个单 一的 P 晶体管作为一个电阻拉向上。同样，故障的 N -网络是从取代的 N -网 络由一个适当大小的单个 N 晶体管。 拟议的门设计可以忍受多个缺陷要么拉或下 拉式网络。为了尽量减少路由开销与重构，一个基于网格的二维路由 控制信号的方法建议。 提议的控制系统可以实现在多晶硅层几乎没有不利影响的 可用性金属层的功能互连。 效力的提议缺损容错技术及其影响电路延迟和功耗进 行了研究。结果表明，该技术对小延迟开销（小于 6 ％ ） ，但所产生漏电功 耗开销（不到 20 ％ ）存在缺陷。
3 。概率校验基于错误 校正[ 5 ] [ 6 ] 。 根据该参考系 2003 年， ！ °放松 requirementof 100 ％正确的设备和互 联可能大幅削减成本的生产，检验和测试。换句话说，这是很难实现 100 ％的 正确性，因为增加了短暂的错误率。
这种增加，假设为驱动的技术推广和侵略性 与降低噪声容限，电源/地反弹，辐射诱导作用，或因永久失败的内部信号线， 很高兴间歇实时刺激。与此同时，古典容错技术都被证明是过于昂贵，用于非关 键应用。按照这一趋势，并观察，对许多 DSP 应用，没有必要维持一个周期的 周期精确计算，只要在系统级的服务质量指标满意或退化在可接受的水平，实时 概率赔偿技术的 DSP 应用的建议。 技术的目的是为了提高服务质量的 DSP 应用， 使用非常少的硬件开销。拟议的概率技术可以弥补错误的组合逻辑电路，以及存 储的内容。 我们的模拟结果表明， 线性过滤器采用拟议的技术， 信噪比改善 13 （分贝） ，可在场的软错误
参考文献：
1 。先生 Ashouei ，答：查特吉，公元辛格和河谷，双佛蒙特州布局方法统计 国际会议的电路设计， 2005 年 10 月， 页。 567 ¨ 泄漏变异最小纳米的 CMOS ， ç 573 。
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4 。先生 Ashouei ，公元辛格答：查特吉，缺陷的容错体系结构为最终的路线 图的 CMOS ，接受欧洲试验研讨会， 2007 年 5 月，德国弗赖堡。
5 。先生 Ashouei ，由巴特查亚，和 A.加特尔吉，概率补偿数字滤波器根据 普适噪音所致的操作员失误，接受试验的 VLSI 研讨会， 2007 年 5 月。
6 。先生 Ashouei ，由巴特查亚，和 A.加特尔吉，提高信噪比为 DSM 的线性 系统利用概率误差校正和国家恢复：比较研究，在欧洲测试研讨会。